Manjusha Sreedharan

Digital Design Intern, Silicon Labs, Singapore May 2022 – Jul 2022

  Designed a ring oscillator which can be scaled using Verilog parameters for TSMC 22nm test chip, emphasizing on a code that can be used for multiple generations.

  Synthesized and verified the design using Cadence Genus and Modelsim Questa to analyze the timing and area which had accuracy greater than 90% with the estimates and also presented a poster at the Silicon Labs Intern Symposium.

Software Developer, Alcatel Lucent Enterprise, Chennai Sep 2020 - Dec 2021

  Collaborated with the team to develop messaging queues with Apache Kafka and pipelines in Confluent platform for the new generation network management system of Alcatel Lucent access points.

  Streamlined the creation of exceptionally reliable micro-services using REST API, Gitlab, Hibernate and Java for the first release.

Graduate Researcher, Department of Electrical Engineering, NUS Singapore Jan 2022 - Present

  Assisted professors from NUS and University of Dublin to work on hardware acceleration for data integrity of wearables by designing and optimizing the hardware using Verilog code.

  Optimized the number of fractional bits used in the fixed point system to get a pareto-optimal points with accuracy of 94%, 96% and 92% in SVM, Binary Decision Tree and Neural Network respectively.

  Analyzed the machine learning models on the Zynq FPGA on different parameters like accuracy, resource utilization, receiver operating characteristics and power consumption.

Undergraduate Researcher, Department of Electronics and Communication Engg, NITPY Aug 2019 – Mar 2020

  Collaborated with another student to build a customized system which recognizes face and text and converts the information to audio to assist visually challenged people, resulting in a publication and presentation at International Virtual Conference on Industry 4.0.

  Systemized using MTCNN for face recognition and Tesseract for text recognition, an accuracy of 100% for still images and 58% for real-time faces was obtained.

Summer Research Fellow, Indian Institute of Space Science and Technology, Thiruvananthapuram, India
Jan 2022 - Present

  Researched on the effect of resistors and capacitors on digital signal conditioning to integrate capacitive sensor measurement with resistive sensors for a new phase and amplitude-based sensing technique and results were presented at the National Conference on Communication Systems (NCOCS-2019).

  The voltage varies 50mV is observed with every 10MΩ change in the resistance value and difference of 1V is obtained 0.2pF capacitance value.

National University of Singapore (NUS) Jan 2022 - Present

  Master of Science in Electrical Engineering

  Current Cumulative Average Point (CAP): 4.5/5.00

  Expected date of graduation: December 2022

  Relevant modules include Embedded Hardware System Design, Integrated Digital Design, VLSI Digital Design,

Analog IC Design, Microelectronics

National Institute of Technology, Puducherry India (NITPY) Aug 2016 - Jun 2020

  Bachelor of Technology in Electronics and Communication Engineering

  Cumulative Grade Point Average (CGPA): 9.3/10

  Relevant modules completed include Digital Circuits, VLSI Design, Semiconductors, Analog Integrated Design,

Electronic Circuits