RAGHURAM JAMBUNATHAN

Globally experienced engineering and semiconductor industry pioneer, seasoned in the execution of leading-edge innovation with multinational electronics enterprises through the balanced management of technical and commercial prerogatives in team-based production environments. A respected industry executive, attuned to the opportunities provided by evolution and breakthrough, able to transition theoretical concepts to functional operational process that support commercial success.

OPEN-SILICON – A semiconductor solutions company providing traditional ASIC design, derivative and platform SoCs, and production handoffs to diverse segments in USA and Europe. Revenue US$60M, ~300 staff.
Director of System-On-Chip Architecture, Bangalore, Karnataka India 2014–2017
Tasked to develop technology strategy, participate in marketing presentations and provide thought leadership in international forums. Given the remit to provide high level technology Advisory to stakeholders, review the architecture of new design starts and design implementation, and operate in a matrix reporting relationship spanning Technical Managers and 90 staff.
• Expertly planned and implemented a roadmap and first-pass success of a High Bandwidth memory, 50% better than current technology. Also supported international roadshows at leading industry business forums, enabling the company to actively pursue the goal of securing 10% of the US$5B Top-End Graphics and AI Chipsets market.
• Attracted leading industry clients to evaluate new generation server chipsets, assisted Marketing Team to identify and
engage prospective customers and maintained a rigorous project review regime with all Engineering Managers.
• Lead a technical advisory engagement to Singapore’s government’s A*STAR for new generation FOWLP Package technology
• Sustained a detailed understanding of market trends and opportunities for the corporate value proposition, injected procurement optimality, scalability and repeatability, and monitored technical team deliverables maintaining standards
and generating proof of deployment.
• Presented at the TSMC Global Innovation Summit 2015 on ‘Innovative Bump Routing Strategy’ at Santa Clara, USA, and co-authored in the TSMC Global Innovation Summit 2016 on ‘High Bandwidth Memory interface’.
 

Tayasaheb Kore Institute of Technology, Shivaji University – Bachelor of Engineering – Electronics, 1994